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CEC1702Q-S1-I/SX (WFBGA-84) — Symbol, Footprint IPC-7351B & 3D STEP Model

CEC1702Q-S1-I/SX

MICROCHIPID: C1136802WFBGA-84 · 84 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CEC1702Q-S1-I/SX (WFBGA-84)A1VCI_OUTA2XTAL2A3IOA3A4XTAL1A5GPIO162/VCI A6IOA6A7IOA7A8GPIO010/I2C0A9GPIO154/I2C0A10IOA10B1BGPO0B2IOB2B3IOB3B4GPIO163/VCI B5GPIO007/I2C0B6IOB6B7GPIO155/I2C0B8GPIO047/KSO0B9GPIO157/LED1B10IOB10C1VTR_PLLC2IOC2C5GPIO045/KSO0C6GPIO127/UARTC9GPIO046/KSO0C10IOC10D1VFLT_PLLD2RESETI#D4VSS_ANALOGD5VBATD6GPIO225/UARTD7GPIO156/LED0D9GPIO104/UARTD10IOD10E1VTR_REGE2IOE2E3VREF_ADCE4VSS1E7GPIO135/UARTE8JTAG RST#_E9GPIO105/UARTE10IOE10K10GPIO053/PWM0K9GPIO026/TIN1K8GPIO040/KSO0K7IOK7K6GPIO056/PWM3K5GPIO223/QSPIK4GPIO227/QSPIK3GPIO224/QSPIK2IOK2K1IOK1J10GPIO027/TIN2J9GPIO054/PWM1J8GPIO031/KSI6J7GPIO017/GPTPJ6GPIO001/PWM4J5GPIO002/PWM5J4GPIO021/KSI2J3GPIO020/KSI1J2IOJ2J1VSS_ADCH10GPIO120/KSO0H9GPIO107/KSO0H6GPIO140/ICT5H5GPIO032/KSI7H2GPIO202/ADC0H1GPIO204/ADC0G10GPIO113/KSO0G9GPIO112/KSO0G7GPIO030/TIN3G6VTR1G5VTR2G4IOG4G2GPIO201/ADC0G1GPIO203/ADC0F10IOF10F9GPIO170/TFCLF8IOF8F7VSS2F4VTR_ANALOGF3IOF3F2GPIO200/ADC0F1VR_CAPGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.858.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4mm
2. 2D FOOTPRINT
A1A2B1A3A5A4A7A6A9A8A10B10B8B9B6B7B4B5B3B2C2C5C6C9C10C1D2D5D4D7D6D9D10D1E2E3E4E7E9E8E10E1F2F3F4F7F9F8F10F1G2G5G4G7G6G9G10G1H2H5H6H9H10H1J2J3J5J4J7J6J9J8J10J1K2K3K5K4K7K6K9K8K10K1E=7.00mm · Pitch e=0.65mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (84/84)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VCI_OUTI/OMultiplexed I/O & Peripheral Pin VCI_OUT (General)
A2XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
A3IOA3I/OGeneral Purpose Digital I/O Pin IOA3
A4XTAL1I/OMultiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)
A5GPIO162/VCI IN1#_I/OMultiplexed I/O & Peripheral Pin GPIO162/VCI IN1#_ (General)
A6IOA6I/OGeneral Purpose Digital I/O Pin IOA6
A7IOA7I/OGeneral Purpose Digital I/O Pin IOA7
A8GPIO010/I2C03_SCLI/OMultiplexed I/O & Peripheral Pin GPIO010/I2C03_SCL (I2C)
A9GPIO154/I2C02_SDAI/OMultiplexed I/O & Peripheral Pin GPIO154/I2C02_SDA (I2C)
A10IOA10I/OGeneral Purpose Digital I/O Pin IOA10
B1BGPO0I/OMultiplexed I/O & Peripheral Pin BGPO0 (General)
B2IOB2I/OGeneral Purpose Digital I/O Pin IOB2
B3IOB3I/OGeneral Purpose Digital I/O Pin IOB3
B4GPIO163/VCI IN0#_I/OMultiplexed I/O & Peripheral Pin GPIO163/VCI IN0#_ (General)
B5GPIO007/I2C03_SDAI/OMultiplexed I/O & Peripheral Pin GPIO007/I2C03_SDA (I2C)
B6IOB6I/OGeneral Purpose Digital I/O Pin IOB6
B7GPIO155/I2C02_SCLI/OMultiplexed I/O & Peripheral Pin GPIO155/I2C02_SCL (I2C)
B8GPIO047/KSO03I/OMultiplexed I/O & Peripheral Pin GPIO047/KSO03 (General)
B9GPIO157/LED1I/OMultiplexed I/O & Peripheral Pin GPIO157/LED1 (General)
B10IOB10I/OGeneral Purpose Digital I/O Pin IOB10
C1VTR_PLLI/OMultiplexed I/O & Peripheral Pin VTR_PLL (General)
C2IOC2I/OGeneral Purpose Digital I/O Pin IOC2
C5GPIO045/KSO01I/OMultiplexed I/O & Peripheral Pin GPIO045/KSO01 (General)
C6GPIO127/UART0 CTS#_I/OMultiplexed I/O & Peripheral Pin GPIO127/UART0 CTS#_ (UART)
C9GPIO046/KSO02I/OMultiplexed I/O & Peripheral Pin GPIO046/KSO02 (General)
C10IOC10I/OGeneral Purpose Digital I/O Pin IOC10
D1VFLT_PLLI/OMultiplexed I/O & Peripheral Pin VFLT_PLL (General)
D2RESETI#ISystem Enable & Hardware Reset (RESETI#)
D4VSS_ANALOGGNDGround Reference Pin (VSS_ANALOG)
D5VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
D6GPIO225/UART0 RTS#_I/OMultiplexed I/O & Peripheral Pin GPIO225/UART0 RTS#_ (UART)
D7GPIO156/LED0I/OMultiplexed I/O & Peripheral Pin GPIO156/LED0 (General)
D9GPIO104/UART0_TXI/OMultiplexed I/O & Peripheral Pin GPIO104/UART0_TX (UART)
D10IOD10I/OGeneral Purpose Digital I/O Pin IOD10
E1VTR_REGI/OMultiplexed I/O & Peripheral Pin VTR_REG (General)
E2IOE2I/OGeneral Purpose Digital I/O Pin IOE2
E3VREF_ADCI/OMultiplexed I/O & Peripheral Pin VREF_ADC (ADC)
E4VSS1GNDGround Reference Pin (VSS1)
E7GPIO135/UART1 CTS#_I/OMultiplexed I/O & Peripheral Pin GPIO135/UART1 CTS#_ (UART)
E8JTAG RST#_I/OMultiplexed I/O & Peripheral Pin JTAG RST#_ (SWD/JTAG)
E9GPIO105/UART0_RXI/OMultiplexed I/O & Peripheral Pin GPIO105/UART0_RX (UART)
E10IOE10I/OGeneral Purpose Digital I/O Pin IOE10
F1VR_CAPI/OMultiplexed I/O & Peripheral Pin VR_CAP (General)
F2GPIO200/ADC00I/OMultiplexed I/O & Peripheral Pin GPIO200/ADC00 (ADC)
F3IOF3I/OGeneral Purpose Digital I/O Pin IOF3
F4VTR_ANALOGI/OMultiplexed I/O & Peripheral Pin VTR_ANALOG (General)
F7VSS2GNDGround Reference Pin (VSS2)
F8IOF8I/OGeneral Purpose Digital I/O Pin IOF8
F9GPIO170/TFCLK/UART1_TXI/OMultiplexed I/O & Peripheral Pin GPIO170/TFCLK/UART1_TX (UART)
F10IOF10I/OGeneral Purpose Digital I/O Pin IOF10
G1GPIO203/ADC03I/OMultiplexed I/O & Peripheral Pin GPIO203/ADC03 (ADC)
G2GPIO201/ADC01I/OMultiplexed I/O & Peripheral Pin GPIO201/ADC01 (ADC)
G4IOG4I/OGeneral Purpose Digital I/O Pin IOG4
G5VTR2I/OMultiplexed I/O & Peripheral Pin VTR2 (General)
G6VTR1I/OMultiplexed I/O & Peripheral Pin VTR1 (General)
G7GPIO030/TIN3/KSI5I/OMultiplexed I/O & Peripheral Pin GPIO030/TIN3/KSI5 (General)
G9GPIO112/KSO05I/OMultiplexed I/O & Peripheral Pin GPIO112/KSO05 (General)
G10GPIO113/KSO06I/OMultiplexed I/O & Peripheral Pin GPIO113/KSO06 (General)
H1GPIO204/ADC04I/OMultiplexed I/O & Peripheral Pin GPIO204/ADC04 (ADC)
H2GPIO202/ADC02I/OMultiplexed I/O & Peripheral Pin GPIO202/ADC02 (ADC)
H5GPIO032/KSI7I/OMultiplexed I/O & Peripheral Pin GPIO032/KSI7 (General)
H6GPIO140/ICT5I/OMultiplexed I/O & Peripheral Pin GPIO140/ICT5 (General)
H9GPIO107/KSO04I/OMultiplexed I/O & Peripheral Pin GPIO107/KSO04 (General)
H10GPIO120/KSO07I/OMultiplexed I/O & Peripheral Pin GPIO120/KSO07 (General)
J1VSS_ADCGNDGround Reference Pin (VSS_ADC)
J2IOJ2I/OGeneral Purpose Digital I/O Pin IOJ2
J3GPIO020/KSI1I/OMultiplexed I/O & Peripheral Pin GPIO020/KSI1 (General)
J4GPIO021/KSI2I/OMultiplexed I/O & Peripheral Pin GPIO021/KSI2 (General)
J5GPIO002/PWM5I/OMultiplexed I/O & Peripheral Pin GPIO002/PWM5 (PWM)
J6GPIO001/PWM4I/OMultiplexed I/O & Peripheral Pin GPIO001/PWM4 (PWM)
J7GPIO017/GPTPIN5/KSI0 -I/OMultiplexed I/O & Peripheral Pin GPIO017/GPTPIN5/KSI0 - (General)
J8GPIO031/KSI6I/OMultiplexed I/O & Peripheral Pin GPIO031/KSI6 (General)
J9GPIO054/PWM1/GPWM1I/OMultiplexed I/O & Peripheral Pin GPIO054/PWM1/GPWM1 (PWM)
J10GPIO027/TIN2/KSI4I/OMultiplexed I/O & Peripheral Pin GPIO027/TIN2/KSI4 (General)
K1IOK1I/OGeneral Purpose Digital I/O Pin IOK1
K2IOK2I/OGeneral Purpose Digital I/O Pin IOK2
K3GPIO224/QSPI0_IO1I/OMultiplexed I/O & Peripheral Pin GPIO224/QSPI0_IO1 (SPI)
K4GPIO227/QSPI0_IO2I/OMultiplexed I/O & Peripheral Pin GPIO227/QSPI0_IO2 (SPI)
K5GPIO223/QSPI0_IO0I/OMultiplexed I/O & Peripheral Pin GPIO223/QSPI0_IO0 (SPI)
K6GPIO056/PWM3/QSPI0_CLKI/OMultiplexed I/O & Peripheral Pin GPIO056/PWM3/QSPI0_CLK (SPI, PWM)
K7IOK7I/OGeneral Purpose Digital I/O Pin IOK7
K8GPIO040/KSO00I/OMultiplexed I/O & Peripheral Pin GPIO040/KSO00 (General)
K9GPIO026/TIN1/KSI3I/OMultiplexed I/O & Peripheral Pin GPIO026/TIN1/KSI3 (General)
K10GPIO053/PWM0/GPWM0I/OMultiplexed I/O & Peripheral Pin GPIO053/PWM0/GPWM0 (PWM)
PIN A1 VCI_OUT
I/O
Multiplexed I/O & Peripheral Pin VCI_OUT (General)
Design note: Signal terminal VCI_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCI_OUT. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CEC1702Q-S1-I/SX (MICROCHIP · WFBGA-84)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CEC1702Q-S1-I/SX (WFBGA-84) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CEC1702Q-S1-I/SX (WFBGA-84) - 2. Standard Pinout (Top View)
True package pinout (84 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CEC1702Q-S1-I/SX (WFBGA-84) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CEC1702Q-S1-I/SX (WFBGA-84) - 4. Package Dimensions (D×E×A)
WFBGA-84 · 7.00×7.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CEC1702Q-S1-I/SX (WFBGA-84) - 5. Recommended Land Pattern
IPC-7351B Footprint (84 Pads)Expand ›
6. Application SchematicSCHEMATIC
CEC1702Q-S1-I/SX (WFBGA-84) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CEC1702
P1 · p01_fig01377×200px
CEC1702Q-S1-I/SX (WFBGA-84) — Cryptographic Embedded Controller
Cryptographic Embedded Controller
P27 · p27_fig011777×2262px
CEC1702Q-S1-I/SX (WFBGA-84) —  2018-2019 Microchip Technology Inc. DS00002207E-page 27 | Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.micro- chip.com/packaging.
 2018-2019 Microchip Technology Inc. DS00002207E-page 27 | Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.micro- chip.com/packaging.
P27 · p27_fig02161×376px
CEC1702Q-S1-I/SX (WFBGA-84) — ;
;
P281 · p281_fig011430×783px
CEC1702Q-S1-I/SX (WFBGA-84) — FIGURE 26-1: I/O DIAGRAM OF BLOCK
FIGURE 26-1: I/O DIAGRAM OF BLOCK
P385 · p385_fig011284×713px
CEC1702Q-S1-I/SX (WFBGA-84) — FIGURE 38-5: CLOCK TIMING DIAGRAM
FIGURE 38-5: CLOCK TIMING DIAGRAM
P385 · p385_fig021786×1510px
CEC1702Q-S1-I/SX (WFBGA-84) —  2018-2019 Microchip Technology Inc. DS00002207E-page 385 | TABLE 38-4: CLOCK TIMING PARAMETERS | Clock Symbol Parameters MIN TYP MAX Units | 48 MHz PLL tSU Start-up accuracy from power-on- reset and waking from Heavy Sleep | - - 3 ms | -
 2018-2019 Microchip Technology Inc. DS00002207E-page 385 | TABLE 38-4: CLOCK TIMING PARAMETERS | Clock Symbol Parameters MIN TYP MAX Units | 48 MHz PLL tSU Start-up accuracy from power-on- reset and waking from Heavy Sleep | - - 3 ms | -
P386 · p386_fig011785×1726px
CEC1702Q-S1-I/SX (WFBGA-84) — FIGURE 38-6: GPIO TIMING
FIGURE 38-6: GPIO TIMING
P386 · p386_fig021536×323px
CEC1702Q-S1-I/SX (WFBGA-84) — FIGURE 38-6: GPIO TIMING
FIGURE 38-6: GPIO TIMING
P386 · p386_fig02P386
CEC1702Q-S1-I/SX (WFBGA-84) — Datasheet Page 386 (p386_fig02)
Datasheet Page 386 (p386_fig02)

Technical Specifications & Part Details (CEC1702Q-S1-I/SX)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CEC1702Q-S1-I/SX (WFBGA-84) is a 84-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.35 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-84)
Pin Count & Lead PitchN / e
84 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol84 auto-grouped pins
OK
IPC-7351B Land Pattern84 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WFBGA-84)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.65mm
Pad Size (W × L)Level B
0.25 × 0.25 mm
Pins / Total PadsTopology
84P / 84Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WFBGA-84
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CEC1702Q-S1-I/SX (WFBGA-84)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CEC1702Q-S1-I/SX (WFBGA-84)?

Manufactured by MICROCHIP, the CEC1702Q-S1-I/SX is housed in a WFBGA-84 package with 84 pins and a 0.65 mm lead pitch. Key pins include: A1 (VCI_OUT: Multiplexed I/O & Peripheral Pin VCI_OUT (General)), A2 (XTAL2: Multiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)), A3 (IOA3: General Purpose Digital I/O Pin IOA3), A4 (XTAL1: Multiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)), A5 (GPIO162/VCI IN1#_: Multiplexed I/O & Peripheral Pin GPIO162/VCI IN1#_ (General)), A6 (IOA6: General Purpose Digital I/O Pin IOA6).

What are the IPC-7351B PCB Footprint dimensions for CEC1702Q-S1-I/SX?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CEC1702Q-S1-I/SX (WFBGA-84) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.65 mm, and 84 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CEC1702Q-S1-I/SX?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CEC1702Q-S1-I/SX (MICROCHIP, WFBGA-84) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (84 pins) & CEC1702 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VCI_OUTDigital_IOSignal terminal VCI_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCI_OUT. Supported peripheral buses: General.
A2XTAL2Digital_IOSignal terminal XTAL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
A3IOA3Digital_IOGeneral Purpose Digital I/O Pin IOA3
A4XTAL1Digital_IOSignal terminal XTAL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK.
A5GPIO162/VCI IN1#_Digital_IOSignal terminal GPIO162/VCI IN1#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO162/VCI IN1#_. Supported peripheral buses: General.
A6IOA6Digital_IOGeneral Purpose Digital I/O Pin IOA6
A7IOA7Digital_IOGeneral Purpose Digital I/O Pin IOA7
A8GPIO010/I2C03_SCLDigital_IOSignal terminal GPIO010/I2C03_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO010/I2C03_SCL. Supported peripheral buses: I2C.
A9GPIO154/I2C02_SDADigital_IOSignal terminal GPIO154/I2C02_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO154/I2C02_SDA. Supported peripheral buses: I2C.
A10IOA10Digital_IOGeneral Purpose Digital I/O Pin IOA10
B1BGPO0Digital_IOSignal terminal BGPO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BGPO0. Supported peripheral buses: General.
B2IOB2Digital_IOGeneral Purpose Digital I/O Pin IOB2
B3IOB3Digital_IOGeneral Purpose Digital I/O Pin IOB3
B4GPIO163/VCI IN0#_Digital_IOSignal terminal GPIO163/VCI IN0#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO163/VCI IN0#_. Supported peripheral buses: General.
B5GPIO007/I2C03_SDADigital_IOSignal terminal GPIO007/I2C03_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO007/I2C03_SDA. Supported peripheral buses: I2C.
B6IOB6Digital_IOGeneral Purpose Digital I/O Pin IOB6
B7GPIO155/I2C02_SCLDigital_IOSignal terminal GPIO155/I2C02_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO155/I2C02_SCL. Supported peripheral buses: I2C.
B8GPIO047/KSO03Digital_IOSignal terminal GPIO047/KSO03 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO047/KSO03. Supported peripheral buses: General.
B9GPIO157/LED1Digital_IOSignal terminal GPIO157/LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO157/LED1. Supported peripheral buses: General.
B10IOB10Digital_IOGeneral Purpose Digital I/O Pin IOB10
C1VTR_PLLDigital_IOSignal terminal VTR_PLL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_PLL. Supported peripheral buses: General.
C2IOC2Digital_IOGeneral Purpose Digital I/O Pin IOC2
C5GPIO045/KSO01Digital_IOSignal terminal GPIO045/KSO01 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO045/KSO01. Supported peripheral buses: General.
C6GPIO127/UART0 CTS#_Digital_IOSignal terminal GPIO127/UART0 CTS#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO127/UART0 CTS#_. Supported peripheral buses: UART.
C9GPIO046/KSO02Digital_IOSignal terminal GPIO046/KSO02 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO046/KSO02. Supported peripheral buses: General.
C10IOC10Digital_IOGeneral Purpose Digital I/O Pin IOC10
D1VFLT_PLLDigital_IOSignal terminal VFLT_PLL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VFLT_PLL. Supported peripheral buses: General.
D2RESETI#Digital_IOActive-low hardware reset terminal (RESETI#): pulling this pin Low resets the processor core and peripherals.
D4VSS_ANALOGGND0V electrical ground return terminal (VSS_ANALOG) for internal core logic, I/O drivers, and analog sub-blocks.
D5VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D6GPIO225/UART0 RTS#_Digital_IOSignal terminal GPIO225/UART0 RTS#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO225/UART0 RTS#_. Supported peripheral buses: UART.
D7GPIO156/LED0Digital_IOSignal terminal GPIO156/LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO156/LED0. Supported peripheral buses: General.
D9GPIO104/UART0_TXDigital_IOSignal terminal GPIO104/UART0_TX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO104/UART0_TX. Supported peripheral buses: UART.
D10IOD10Digital_IOGeneral Purpose Digital I/O Pin IOD10
E1VTR_REGDigital_IOSignal terminal VTR_REG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_REG. Supported peripheral buses: General.
E2IOE2Digital_IOGeneral Purpose Digital I/O Pin IOE2
E3VREF_ADCAnalogSignal terminal VREF_ADC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF_ADC. Supported peripheral buses: ADC.
E4VSS1GND0V electrical ground return terminal (VSS1) for internal core logic, I/O drivers, and analog sub-blocks.
E7GPIO135/UART1 CTS#_Digital_IOSignal terminal GPIO135/UART1 CTS#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO135/UART1 CTS#_. Supported peripheral buses: UART.
E8JTAG RST#_Digital_IOSignal terminal JTAG RST#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: JTAG RST#_. Supported peripheral buses: SWD/JTAG.
E9GPIO105/UART0_RXDigital_IOSignal terminal GPIO105/UART0_RX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO105/UART0_RX. Supported peripheral buses: UART.
E10IOE10Digital_IOGeneral Purpose Digital I/O Pin IOE10
F1VR_CAPDigital_IOSignal terminal VR_CAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VR_CAP. Supported peripheral buses: General.
F2GPIO200/ADC00AnalogSignal terminal GPIO200/ADC00 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO200/ADC00. Supported peripheral buses: ADC.
F3IOF3Digital_IOGeneral Purpose Digital I/O Pin IOF3
F4VTR_ANALOGDigital_IOSignal terminal VTR_ANALOG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_ANALOG. Supported peripheral buses: General.
F7VSS2GND0V electrical ground return terminal (VSS2) for internal core logic, I/O drivers, and analog sub-blocks.
F8IOF8Digital_IOGeneral Purpose Digital I/O Pin IOF8
F9GPIO170/TFCLK/UART1_TXDigital_IOSignal terminal GPIO170/TFCLK/UART1_TX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO170/TFCLK/UART1_TX. Supported peripheral buses: UART.
F10IOF10Digital_IOGeneral Purpose Digital I/O Pin IOF10
G1GPIO203/ADC03AnalogSignal terminal GPIO203/ADC03 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO203/ADC03. Supported peripheral buses: ADC.
G2GPIO201/ADC01AnalogSignal terminal GPIO201/ADC01 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO201/ADC01. Supported peripheral buses: ADC.
G4IOG4Digital_IOGeneral Purpose Digital I/O Pin IOG4
G5VTR2Digital_IOSignal terminal VTR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR2. Supported peripheral buses: General.
G6VTR1Digital_IOSignal terminal VTR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR1. Supported peripheral buses: General.
G7GPIO030/TIN3/KSI5Digital_IOSignal terminal GPIO030/TIN3/KSI5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO030/TIN3/KSI5. Supported peripheral buses: General.
G9GPIO112/KSO05Digital_IOSignal terminal GPIO112/KSO05 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO112/KSO05. Supported peripheral buses: General.
G10GPIO113/KSO06Digital_IOSignal terminal GPIO113/KSO06 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO113/KSO06. Supported peripheral buses: General.
H1GPIO204/ADC04AnalogSignal terminal GPIO204/ADC04 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO204/ADC04. Supported peripheral buses: ADC.
H2GPIO202/ADC02AnalogSignal terminal GPIO202/ADC02 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO202/ADC02. Supported peripheral buses: ADC.
H5GPIO032/KSI7Digital_IOSignal terminal GPIO032/KSI7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO032/KSI7. Supported peripheral buses: General.
H6GPIO140/ICT5Digital_IOSignal terminal GPIO140/ICT5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO140/ICT5. Supported peripheral buses: General.
H9GPIO107/KSO04Digital_IOSignal terminal GPIO107/KSO04 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO107/KSO04. Supported peripheral buses: General.
H10GPIO120/KSO07Digital_IOSignal terminal GPIO120/KSO07 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO120/KSO07. Supported peripheral buses: General.
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