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STM32WLE5CBU6 (UFQFPN-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WLE5CBU6

STID: C1121847UFQFPN-48(7x7) · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WLE5CBU6 (UFQFPN-48(7x7))1PB32PB43PB54PB65PB768 -Jul -20207PA089 -Nov-20209PA210PA311VDD12PA413PA514PA615PA716PA817PA918NRST19PH3 BOOT0 -20RFI_P21RFI_N22RFO_LP23RFO_HP24VR_PA25VDDPA49EP48VSSSMPS47VLXSMPS46VDDSMPS45VFBSMPS44VDD43PA1542PA1441VDDA40PC15 - OSC3239PC14OSC32 IN38PC1337VBAT36PA1335PA1234PA1133PA1032PB1231PB230PB0VDD TCXO 29VDDRF1V5528VDDRF27OSC_OUT26OSC_INGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PB3I/OMultiplexed I/O & Peripheral Pin PB3 (ADC, PWM, SWD/JTAG)
2PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, I2C, ADC, SWD/JTAG)
3PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI)
4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
68 -Jul -2020I/OMultiplexed I/O & Peripheral Pin 8 -Jul -2020 (General)
7PA0I/OMultiplexed I/O & Peripheral Pin PA0 (PWM)
89 -Nov-2020I/OMultiplexed I/O & Peripheral Pin 9 -Nov-2020 (General)
9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART)
10PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, PWM)
11VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
12PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, RTC/CLK)
13PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, PWM)
14PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI)
15PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, PWM)
16PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, RTC/CLK)
17PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, I2C, PWM)
18NRSTISystem Enable & Hardware Reset (NRST)
19PH3 BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3 BOOT0 - (General)
20RFI_PI/OMultiplexed I/O & Peripheral Pin RFI_P (General)
21RFI_NI/OMultiplexed I/O & Peripheral Pin RFI_N (General)
22RFO_LPI/OMultiplexed I/O & Peripheral Pin RFO_LP (General)
23RFO_HPI/OMultiplexed I/O & Peripheral Pin RFO_HP (General)
24VR_PAI/OMultiplexed I/O & Peripheral Pin VR_PA (General)
25VDDPAPowerPower Supply Input (VDDPA — 3.3V VDD (Max 4.0V))
26OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
27OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
28VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
29VDDRF1V55PowerPower Supply Input (VDDRF1V55 — 3.3V VDD (Max 4.0V))
30PB0VDD TCXO -_PowerRegulated Power Output (PB0VDD TCXO -_ — 3.3V VDD (Max 4.0V))
31PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, ADC)
32PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
33PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, SPI, I2C, ADC, DAC, RTC/CLK)
34PA11I/OMultiplexed I/O & Peripheral Pin PA11 (SPI, ADC, PWM)
35PA12I/OMultiplexed I/O & Peripheral Pin PA12 (I2C, ADC)
36PA13I/OMultiplexed I/O & Peripheral Pin PA13 (I2C, ADC, SWD/JTAG)
37VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
38PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
39PC14OSC32 IN -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)
40PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
41VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
42PA14I/OMultiplexed I/O & Peripheral Pin PA14 (I2C, ADC, SWD/JTAG)
43PA15I/OMultiplexed I/O & Peripheral Pin PA15 (I2C, ADC, SWD/JTAG)
44VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
45VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
46VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
47VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
48VSSSMPSGNDGround Reference Pin (VSSSMPS)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PB3
I/O
Multiplexed I/O & Peripheral Pin PB3 (ADC, PWM, SWD/JTAG)
Design note: Alt: JTDO/TRACESWO , TIM2_CH2SPI1SCK ,_ , RF_IRQ0USART1RTS ,_ , DEBUG_RFDTB1_ , CM4_EVENTOUT | Add: COMP1_INM , COMP2_INM , ADC_IN2 , TAMP IN3/WKUP3_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WLE5CBU6 (ST · UFQFPN-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WLE5CBU6 (UFQFPN-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WLE5CBU6 (UFQFPN-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WLE5CBU6 (UFQFPN-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WLE5CBU6 (UFQFPN-48(7x7)) - 4. Package Dimensions (D×E×A)
UFQFPN-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WLE5CBU6 (UFQFPN-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WLE5CBU6 (UFQFPN-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for STM32WLE4C8U / STM32WLE5CBU / STM32WLE5J8I
P49 · p49_fig01EXACT PACKAGE
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Figure 9. UFQFPN48 pinout
Figure 9. UFQFPN48 pinout
P135 · p135_fig01EXACT PACKAGE
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Figure 31. UFQFPN48 - Recommended footprint
Figure 31. UFQFPN48 - Recommended footprint
P1 · p01_fig01881×483px
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®,
Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®,
P49 · p49_fig01P49
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Datasheet Page 49 (p49_fig01)
Datasheet Page 49 (p49_fig01)
P62 · p62_fig011546×1883px
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Figure 13. Power supply scheme VBAT
Figure 13. Power supply scheme VBAT
P62 · p62_fig01P62
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Datasheet Page 62 (p62_fig01)
Datasheet Page 62 (p62_fig01)
P119 · p119_fig011547×641px
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Figure 23. Typical connection diagram using the ADC
Figure 23. Typical connection diagram using the ADC
P135 · p135_fig01P135
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Datasheet Page 135 (p135_fig01)
Datasheet Page 135 (p135_fig01)
P138 · p138_fig011546×718px
STM32WLE5CBU6 (UFQFPN-48(7x7)) — Figure 34. UFBGA73 - Recommended footprint
Figure 34. UFBGA73 - Recommended footprint

Technical Specifications & Part Details (STM32WLE5CBU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WLE5CBU6 (UFQFPN-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8 V to 3.6 V supply operation across 40 °C to +105 °C with integrated UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40 °C to +105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
150 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
27 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.55 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3 BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.50×5.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.55 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WLE5CBU6 (UFQFPN-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WLE5CBU6 (UFQFPN-48(7x7))?

Manufactured by ST, the STM32WLE5CBU6 is housed in a UFQFPN-48(7x7) package with 49 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8 V to 3.6 V. Key pins include: 1 (PB3: Multiplexed I/O & Peripheral Pin PB3 (ADC, PWM, SWD/JTAG)), 2 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI, I2C, ADC, SWD/JTAG)), 3 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI)), 4 (PB6: Multiplexed I/O & Peripheral Pin PB6 (UART)), 5 (PB7: Multiplexed I/O & Peripheral Pin PB7 (I2C)), 6 (8 -Jul -2020: Multiplexed I/O & Peripheral Pin 8 -Jul -2020 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32WLE5CBU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WLE5CBU6 (UFQFPN-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.50 × 5.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WLE5CBU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WLE5CBU6 (ST, UFQFPN-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32WLE4C8U / STM32WLE5CBU / STM32WLE5J8I Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: ADC, PWM, SWD/JTAG.
2PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, I2C, ADC, SWD/JTAG.
3PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSIRFIRQ1. Supported peripheral buses: UART, SPI.
4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
68 -Jul -2020Digital_IOSignal terminal 8 -Jul -2020 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 8 -Jul -2020. Supported peripheral buses: General.
7PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: PWM.
89 -Nov-2020Digital_IOSignal terminal 9 -Nov-2020 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: 9 -Nov-2020. Supported peripheral buses: General.
9PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART.
10PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, PWM.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
12PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSUSART2CK. Supported peripheral buses: SPI, RTC/CLK.
13PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOSPI1SCK. Supported peripheral buses: SPI, PWM.
14PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOLPUART1CTS. Supported peripheral buses: SPI.
15PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSICOMP2OUT. Supported peripheral buses: SPI, PWM.
16PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, RTC/CLK.
17PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C1_SCL, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
18NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
19PH3 BOOT0 -Digital_IOSignal terminal PH3 BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3 BOOT0 -. Supported peripheral buses: General.
20RFI_PRF_50OhmSignal terminal RFI_P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RFI_P. Supported peripheral buses: General.
21RFI_NRF_50OhmSignal terminal RFI_N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RFI_N. Supported peripheral buses: General.
22RFO_LPRF_50OhmSignal terminal RFO_LP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RFO_LP. Supported peripheral buses: General.
23RFO_HPRF_50OhmSignal terminal RFO_HP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RFO_HP. Supported peripheral buses: General.
24VR_PADigital_IOSignal terminal VR_PA (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VR_PA. Supported peripheral buses: General.
25VDDPAPower_InPrimary positive power supply input (VDDPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
26OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
27OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
28VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
29VDDRF1V55Power_InPrimary positive power supply input (VDDRF1V55) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
30PB0VDD TCXO -_Power_OutRegulated power output rail (PB0VDD TCXO -_) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
31PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC.
32PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI.
33PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_MOSI. Supported peripheral buses: UART, SPI, I2C, ADC, DAC, RTC/CLK.
34PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, ADC, PWM.
35PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: I2C, ADC.
36PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA. Supported peripheral buses: I2C, ADC, SWD/JTAG.
37VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
38PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
39PC14OSC32 IN -_Digital_IOSignal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK.
40PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
41VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
42PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA. Supported peripheral buses: I2C, ADC, SWD/JTAG.
43PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: I2C, ADC, SWD/JTAG.
44VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
45VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
46VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
47VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
48VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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