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STM32F301K8U6 (UFQFPN-32(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F301K8U6

STID: C111684UFQFPN-32(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F301K8U6 (UFQFPN-32(5x5))1VDD_12PF0OSC IN(PF3PF1OSC OUT(P4NRST5VDDA/VREF+6VSSA/VREF -7PA0 TAMPER2W8PA19PA210PA311PA412PA513PA614PA715PB016VSS_217VDD_233EP32VSS_131BOOT030PB729PB628PB527PB426PB325PA1524PA1423PA1322PA1221PA1120PA1019PA918PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
2PF0OSC IN(PF0)_I/OMultiplexed I/O & Peripheral Pin PF0OSC IN(PF0)_ (SPI, I2C, PWM)
3PF1OSC OUT(PF1)_I/OMultiplexed I/O & Peripheral Pin PF1OSC OUT(PF1)_ (SPI, I2C)
4NRSTISystem Enable & Hardware Reset (NRST)
5VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))
6VSSA/VREF -GNDGround Reference Pin (VSSA/VREF -)
7PA0 TAMPER2WKUP1 - -I/OMultiplexed I/O & Peripheral Pin PA0 TAMPER2WKUP1 - - (General)
8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, RTC/CLK)
9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART)
10PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART)
11PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI)
12PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
13PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
14PA7I/OMultiplexed I/O & Peripheral Pin PA7 (PWM)
15PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
16VSS_2GNDGround Reference Pin (VSS_2)
17VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, RTC/CLK)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, PWM)
20PA10I/OMultiplexed I/O & Peripheral Pin PA10 (SPI, I2C, PWM)
21PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI)
22PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
23PA13I/OMultiplexed I/O & Peripheral Pin PA13 (UART, SWD/JTAG)
24PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, I2C, SWD/JTAG)
25PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
26PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI, SWD/JTAG)
27PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART, SPI)
28PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
29PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
30PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
31BOOT0IInput-Only Pin BOOT0 (General)
32VSS_1GNDGround Reference Pin (VSS_1)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDD_1
Power
Power Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
Design note: 数字电源
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F301K8U6 (ST · UFQFPN-32(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F301K8U6 (UFQFPN-32(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F301K8U6 (UFQFPN-32(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F301K8U6 (UFQFPN-32(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F301K8U6 (UFQFPN-32(5x5)) - 4. Package Dimensions (D×E×A)
UFQFPN-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F301K8U6 (UFQFPN-32(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F301K8U6 (UFQFPN-32(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for STM32F301
P31 · p31_fig01EXACT PACKAGE
STM32F301K8U6 (UFQFPN-32(5x5)) — 图 4. STM32F301x6/8 UFQFN32 引脚排列
图 4. STM32F301x6/8 UFQFN32 引脚排列
P1 · p01_fig01881×423px
STM32F301K8U6 (UFQFPN-32(5x5)) — - VDD、VDDA 电压范围：2.0 至3.6 V - 开机/ 关机复位（POR/PDR） - 可编程电压检测器 (PVD) - 低功耗：睡眠、停止、待机 - VBAT 为 RTC 和备份寄存器供电
- VDD、VDDA 电压范围：2.0 至3.6 V - 开机/ 关机复位（POR/PDR） - 可编程电压检测器 (PVD) - 低功耗：睡眠、停止、待机 - VBAT 为 RTC 和备份寄存器供电
P1 · p01_fig02883×285px
STM32F301K8U6 (UFQFPN-32(5x5)) — • 1 单元运算放大器，可用于PGA 模式，所有终 端访问的模拟供电为2.4 至3.6 V
• 1 单元运算放大器，可用于PGA 模式，所有终 端访问的模拟供电为2.4 至3.6 V
P31 · p31_fig01P31
STM32F301K8U6 (UFQFPN-32(5x5)) — Datasheet Page 31 (p31_fig01)
Datasheet Page 31 (p31_fig01)
P75 · p75_fig011546×763px
STM32F301K8U6 (UFQFPN-32(5x5)) — 图 16. 采用 8 MHz 晶振的典型应用
图 16. 采用 8 MHz 晶振的典型应用
P75 · p75_fig01P75
STM32F301K8U6 (UFQFPN-32(5x5)) — Datasheet Page 75 (p75_fig01)
Datasheet Page 75 (p75_fig01)
P77 · p77_fig011546×709px
STM32F301K8U6 (UFQFPN-32(5x5)) — 图 17. 采用 32.768 kHz 晶振的典型应用
图 17. 采用 32.768 kHz 晶振的典型应用
P31 · p31_fig02All Packages in PDF
STM32F301K8U6 (UFQFPN-32(5x5)) — 图 5. STM32F301x6/8 LQFP48 引脚排列
图 5. STM32F301x6/8 LQFP48 引脚排列

Technical Specifications & Part Details (STM32F301K8U6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F301K8U6 (UFQFPN-32(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.60 mm (A1=0.03 mm)
Package family: QFN (UFQFPN-32(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.45×3.45mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-32(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F301K8U6 (UFQFPN-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F301K8U6 (UFQFPN-32(5x5))?

Manufactured by ST, the STM32F301K8U6 is housed in a UFQFPN-32(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD_1: Power Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))), 2 (PF0OSC IN(PF0)_: Multiplexed I/O & Peripheral Pin PF0OSC IN(PF0)_ (SPI, I2C, PWM)), 3 (PF1OSC OUT(PF1)_: Multiplexed I/O & Peripheral Pin PF1OSC OUT(PF1)_ (SPI, I2C)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VDDA/VREF+: Power Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))), 6 (VSSA/VREF -: Ground Reference Pin (VSSA/VREF -)).

What are the IPC-7351B PCB Footprint dimensions for STM32F301K8U6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F301K8U6 (UFQFPN-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.45 × 3.45 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F301K8U6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F301K8U6 (ST, UFQFPN-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32F301 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PF0OSC IN(PF0)_Digital_IOSignal terminal PF0OSC IN(PF0)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA, SPI2_NSS. Supported peripheral buses: SPI, I2C, PWM.
3PF1OSC OUT(PF1)_Digital_IOSignal terminal PF1OSC OUT(PF1)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCK. Supported peripheral buses: SPI, I2C.
4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6VSSA/VREF -GND0V electrical ground return terminal (VSSA/VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
7PA0 TAMPER2WKUP1 - -Digital_IOSignal terminal PA0 TAMPER2WKUP1 - - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0 TAMPER2WKUP1 - -. Supported peripheral buses: General.
8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, RTC/CLK.
9PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART.
10PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART.
11PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: UART, SPI.
12PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
13PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
14PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: PWM.
15PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
16VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
17VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C3_SCL, I2C2_SMBAL. Supported peripheral buses: UART, I2C, RTC/CLK.
19PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C, PWM.
20PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA, SPI2_MISO. Supported peripheral buses: SPI, I2C, PWM.
21PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
22PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
23PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: UART, SWD/JTAG.
24PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, I2C, SWD/JTAG.
25PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
26PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, SWD/JTAG.
27PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
28PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, I2C.
29PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C.
30PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
31BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
32VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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