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CH423S (SOP-28-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH423S

WCHID: C111663SOP-28-300mil · 28 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH423S (SOP-28-300mil)1IO52IO63IO74OC05OC16SCL7SDA8OC49SCL10SDA11GND12OC513OC614OC728INT#27IO326IO225VCC24IO123IO022OC1521VCC20IO0～IO719IO0～IO718OC1117OC1016OC915OC8Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=7.50mm · Pitch e=1.27mmD=17.90mm-10-8-6-4-20246810131197531-1-3-5-7-9-11-13mm
3. 3D CAD MODEL
Package Body: 7.50mm × 17.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO5I/OMultiplexed I/O & Peripheral Pin IO5 (General)
2IO6I/OMultiplexed I/O & Peripheral Pin IO6 (General)
3IO7I/OMultiplexed I/O & Peripheral Pin IO7 (General)
4OC0I/OMultiplexed I/O & Peripheral Pin OC0 (General)
5OC1I/OMultiplexed I/O & Peripheral Pin OC1 (General)
6SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
7SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
8OC4I/OMultiplexed I/O & Peripheral Pin OC4 (General)
9SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
10SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
11GNDGNDGround Reference Pin (GND)
12OC5I/OMultiplexed I/O & Peripheral Pin OC5 (General)
13OC6I/OMultiplexed I/O & Peripheral Pin OC6 (General)
14OC7I/OMultiplexed I/O & Peripheral Pin OC7 (General)
15OC8I/OMultiplexed I/O & Peripheral Pin OC8 (General)
16OC9I/OMultiplexed I/O & Peripheral Pin OC9 (General)
17OC10I/OMultiplexed I/O & Peripheral Pin OC10 (General)
18OC11I/OMultiplexed I/O & Peripheral Pin OC11 (General)
19IO0～IO7I/OMultiplexed I/O & Peripheral Pin IO0～IO7 (General)
20IO0～IO7I/OMultiplexed I/O & Peripheral Pin IO0～IO7 (General)
21VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
22OC15I/OMultiplexed I/O & Peripheral Pin OC15 (General)
23IO0I/OMultiplexed I/O & Peripheral Pin IO0 (General)
24IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
25VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
26IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
27IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
28INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
PIN 1 IO5
I/O
Multiplexed I/O & Peripheral Pin IO5 (General)
Design note: Signal terminal IO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH423S (WCH · SOP-28-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH423S (SOP-28-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH423S (SOP-28-300mil) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH423S (SOP-28-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH423S (SOP-28-300mil) - 4. Package Dimensions (D×E×A)
SOP-28-300mil · 7.50×17.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH423S (SOP-28-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH423S (SOP-28-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH423
P2 · p02_fig01EXACT PACKAGE
CH423S (SOP-28-300mil) — 封装形式 塑体宽度 引脚节距 封装说明 订货型号 QFN28 4*4mm 0.4mm 15.7mil 方形无引线28 脚 CH423F SOP28 7.62mm 300mil 1.27mm 50mil 标准的28 脚贴片 CH423S DIP28S SK-DIP28 7.62mm 300mil 2.54mm 100mil 窄28 脚双列直插 CH423A
封装形式 塑体宽度 引脚节距 封装说明 订货型号 QFN28 4*4mm 0.4mm 15.7mil 方形无引线28 脚 CH423F SOP28 7.62mm 300mil 1.27mm 50mil 标准的28 脚贴片 CH423S DIP28S SK-DIP28 7.62mm 300mil 2.54mm 100mil 窄28 脚双列直插 CH423A
P1 · p01_fig011615×836px
CH423S (SOP-28-300mil) — 2、特点
2、特点
P2 · p02_fig01P2
CH423S (SOP-28-300mil) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P8 · p08_fig011491×451px
CH423S (SOP-28-300mil) — 8、应用
8、应用
P8 · p08_fig021344×743px
CH423S (SOP-28-300mil) — 8.2. 动态显示驱动（下图）
8.2. 动态显示驱动（下图）
P8 · p08_fig02P8
CH423S (SOP-28-300mil) — Datasheet Page 8 (p08_fig02)
Datasheet Page 8 (p08_fig02)
P9 · p09_fig011728×1164px
CH423S (SOP-28-300mil) — 8.3. 数字电位器（下图）
8.3. 数字电位器（下图）
P9 · p09_fig021089×1057px
CH423S (SOP-28-300mil) — CH423 的OC 引脚在开漏输出方式下是低阻开漏输出，导通电阻小于10 欧姆，可以用作一端接地 的模拟开关，多个OC 引脚各自外接电阻并组合导通后，可以构成一端接地的数字可编程电阻。
CH423 的OC 引脚在开漏输出方式下是低阻开漏输出，导通电阻小于10 欧姆，可以用作一端接地 的模拟开关，多个OC 引脚各自外接电阻并组合导通后，可以构成一端接地的数字可编程电阻。
P10 · p10_fig011637×564px
CH423S (SOP-28-300mil) — 8.5. 单片机接口程序
8.5. 单片机接口程序

Technical Specifications & Part Details (CH423S)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH423S (SOP-28-300mil) is a 28-pin standard electronic & interconnect component featuring a 17.90 × 7.50 × 2.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
17.90 × 7.50 × 2.50 mm (A1=0.20 mm)
Package family: SOP (SOP-28-300mil)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (IO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-28-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
17.90 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-28-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH423S (SOP-28-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH423S (SOP-28-300mil)?

Manufactured by WCH, the CH423S is housed in a SOP-28-300mil package with 28 pins and a 1.27 mm lead pitch. Key pins include: 1 (IO5: Multiplexed I/O & Peripheral Pin IO5 (General)), 2 (IO6: Multiplexed I/O & Peripheral Pin IO6 (General)), 3 (IO7: Multiplexed I/O & Peripheral Pin IO7 (General)), 4 (OC0: Multiplexed I/O & Peripheral Pin OC0 (General)), 5 (OC1: Multiplexed I/O & Peripheral Pin OC1 (General)), 6 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)).

What are the IPC-7351B PCB Footprint dimensions for CH423S?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH423S (SOP-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH423S?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH423S (WCH, SOP-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & CH423 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO5Digital_IOSignal terminal IO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
2IO6Digital_IOSignal terminal IO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO6. Supported peripheral buses: General.
3IO7Digital_IOSignal terminal IO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO7. Supported peripheral buses: General.
4OC0Digital_IOSignal terminal OC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC0. Supported peripheral buses: General.
5OC1Digital_IOSignal terminal OC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC1. Supported peripheral buses: General.
6SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
7SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
8OC4Digital_IOSignal terminal OC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC4. Supported peripheral buses: General.
9SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
10SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
11GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
12OC5Digital_IOSignal terminal OC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC5. Supported peripheral buses: General.
13OC6Digital_IOSignal terminal OC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC6. Supported peripheral buses: General.
14OC7Digital_IOSignal terminal OC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC7. Supported peripheral buses: General.
15OC8Digital_IOSignal terminal OC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC8. Supported peripheral buses: General.
16OC9Digital_IOSignal terminal OC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC9. Supported peripheral buses: General.
17OC10Digital_IOSignal terminal OC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC10. Supported peripheral buses: General.
18OC11Digital_IOSignal terminal OC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC11. Supported peripheral buses: General.
19IO0～IO7Digital_IOSignal terminal IO0～IO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0～IO7. Supported peripheral buses: General.
20IO0～IO7Digital_IOSignal terminal IO0～IO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0～IO7. Supported peripheral buses: General.
21VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22OC15Digital_IOSignal terminal OC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC15. Supported peripheral buses: General.
23IO0Digital_IOSignal terminal IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
24IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
25VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
27IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
28INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
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