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CH9350L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9350L

WCHID: C109472LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9350L (LQFP-48(7x7))1LED12LED23RST4S05S16XOSC7DEBUG8NC9NC10NC11NC12NC13NC14NC15NC16XI17XO18VSS/GND19NC20NC21IO122IO223IO324IO448LED047NC46NC45SEL44NC43NC42VDD3341VIN540NC39NC38BAUD037BAUD136NC35NC34NC33NC32DM31DP30HM29HP28TXD27RXD26TNOW25NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1LED1I/OMultiplexed I/O & Peripheral Pin LED1 (General)
2LED2I/OMultiplexed I/O & Peripheral Pin LED2 (General)
3RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
4S0I/OMultiplexed I/O & Peripheral Pin S0 (General)
5S1I/OMultiplexed I/O & Peripheral Pin S1 (General)
6XOSCI/OMultiplexed I/O & Peripheral Pin XOSC (RTC/CLK)
7DEBUGI/OMultiplexed I/O & Peripheral Pin DEBUG (General)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
10NCI/OMultiplexed I/O & Peripheral Pin NC (General)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
17XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
18VSS/GNDGNDGround Reference Pin (VSS/GND)
19NCI/OMultiplexed I/O & Peripheral Pin NC (General)
20NCI/OMultiplexed I/O & Peripheral Pin NC (General)
21IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
22IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
23IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
24IO4I/OMultiplexed I/O & Peripheral Pin IO4 (General)
25NCI/OMultiplexed I/O & Peripheral Pin NC (General)
26TNOWI/OMultiplexed I/O & Peripheral Pin TNOW (General)
27RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
28TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
29HPI/OMultiplexed I/O & Peripheral Pin HP (General)
30HMI/OMultiplexed I/O & Peripheral Pin HM (General)
31DPI/OMultiplexed I/O & Peripheral Pin DP (General)
32DMI/OMultiplexed I/O & Peripheral Pin DM (General)
33NCI/OMultiplexed I/O & Peripheral Pin NC (General)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35NCI/OMultiplexed I/O & Peripheral Pin NC (General)
36NCI/OMultiplexed I/O & Peripheral Pin NC (General)
37BAUD1I/OMultiplexed I/O & Peripheral Pin BAUD1 (General)
38BAUD0I/OMultiplexed I/O & Peripheral Pin BAUD0 (General)
39NCI/OMultiplexed I/O & Peripheral Pin NC (General)
40NCI/OMultiplexed I/O & Peripheral Pin NC (General)
41VIN5PowerPower Supply Input (VIN5 — 3.3V / 5.0V Standard Logic)
42VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
43NCI/OMultiplexed I/O & Peripheral Pin NC (General)
44NCI/OMultiplexed I/O & Peripheral Pin NC (General)
45SELI/OMultiplexed I/O & Peripheral Pin SEL (General)
46NCI/OMultiplexed I/O & Peripheral Pin NC (General)
47NCI/OMultiplexed I/O & Peripheral Pin NC (General)
48LED0I/OMultiplexed I/O & Peripheral Pin LED0 (General)
PIN 1 LED1
I/O
Multiplexed I/O & Peripheral Pin LED1 (General)
Design note: Signal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9350L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9350L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9350L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9350L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9350L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9350L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9350L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH9350
P1 · p01_fig011679×1177px
CH9350L (LQFP-48(7x7)) — 2、 应用于KVM 延长+切换，或者矩阵式切换使用（多对键盘鼠标在多台主机上使用情况）， 多使用工作状态2，该状态支持多对不同的键盘鼠标对应多台主机的使用；
2、 应用于KVM 延长+切换，或者矩阵式切换使用（多对键盘鼠标在多台主机上使用情况）， 多使用工作状态2，该状态支持多对不同的键盘鼠标对应多台主机的使用；
P3 · p03_fig011715×2363px
CH9350L (LQFP-48(7x7)) — LED0 48 | LED1 1 | LED2 2 | RST 3 | S0 4 | xOSC 6 | DEBUG 7 | XI 16 XO 17 VSS/GND 18 | TNOW 26 RXD 27 TXD 28 HP 29 HM 30 DP 31 DM 32 | BAUD1 37 | BAUD0 38 | VIN5 41 | VDD33 42 | SEL 45 | S1 5 | NC 8 | NC 9 | NC 10 | NC 11 | NC 12 | NC 15 |
LED0 48 | LED1 1 | LED2 2 | RST 3 | S0 4 | xOSC 6 | DEBUG 7 | XI 16 XO 17 VSS/GND 18 | TNOW 26 RXD 27 TXD 28 HP 29 HM 30 DP 31 DM 32 | BAUD1 37 | BAUD0 38 | VIN5 41 | VDD33 42 | SEL 45 | S1 5 | NC 8 | NC 9 | NC 10 | NC 11 | NC 12 | NC 15 |
P7 · p07_fig011713×1395px
CH9350L (LQFP-48(7x7)) — 图7-1 下位机模式
图7-1 下位机模式
P7 · p07_fig01P7
CH9350L (LQFP-48(7x7)) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P8 · p08_fig011713×1395px
CH9350L (LQFP-48(7x7)) — 图7-2 上位机模式
图7-2 上位机模式

Technical Specifications & Part Details (CH9350L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9350L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9350L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9350L (LQFP-48(7x7))?

Manufactured by WCH, the CH9350L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (LED1: Multiplexed I/O & Peripheral Pin LED1 (General)), 2 (LED2: Multiplexed I/O & Peripheral Pin LED2 (General)), 3 (RST: Multiplexed I/O & Peripheral Pin RST (General)), 4 (S0: Multiplexed I/O & Peripheral Pin S0 (General)), 5 (S1: Multiplexed I/O & Peripheral Pin S1 (General)), 6 (XOSC: Multiplexed I/O & Peripheral Pin XOSC (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH9350L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9350L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9350L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9350L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH9350 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1LED1Digital_IOSignal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General.
2LED2Digital_IOSignal terminal LED2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2. Supported peripheral buses: General.
3RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
4S0Digital_IOSignal terminal S0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S0. Supported peripheral buses: General.
5S1Digital_IOSignal terminal S1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1. Supported peripheral buses: General.
6XOSCDigital_IOSignal terminal XOSC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XOSC. Supported peripheral buses: RTC/CLK.
7DEBUGDigital_IOSignal terminal DEBUG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DEBUG. Supported peripheral buses: General.
8NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
17XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
18VSS/GNDGND0V electrical ground return terminal (VSS/GND) for internal core logic, I/O drivers, and analog sub-blocks.
19NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
21IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
22IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
23IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
24IO4Digital_IOSignal terminal IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
25NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
26TNOWDigital_IOSignal terminal TNOW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW. Supported peripheral buses: General.
27RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
28TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
29HPDigital_IOSignal terminal HP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HP. Supported peripheral buses: General.
30HMDigital_IOSignal terminal HM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HM. Supported peripheral buses: General.
31DPDigital_IOSignal terminal DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP. Supported peripheral buses: General.
32DMDigital_IOSignal terminal DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM. Supported peripheral buses: General.
33NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
34NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
36NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
37BAUD1Digital_IOSignal terminal BAUD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BAUD1. Supported peripheral buses: General.
38BAUD0Digital_IOSignal terminal BAUD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BAUD0. Supported peripheral buses: General.
39NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
40NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
41VIN5Power_InPrimary positive power supply input (VIN5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
42VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
44NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
45SELDigital_IOSignal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: General.
46NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
47NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
48LED0Digital_IOSignal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General.
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