ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH446Q (LQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH446Q

WCHID: C109471LQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH446Q (LQFP-44(10x10))1Y0 X3 -2X0～X233X64X0～X235X86X97X108X0～X239NC10P/ S -11X0～X2312GND13Y614STB15Y516VEE17Y418AX119Y0～Y420Y0～Y421AY122NC44NC .43AX042Y0～Y441RST40NC .39X0～X2338VDD37Y236DAT35Y134CS/CK33Y032NC .31X030X129X228X0～X2327X426X525X1224X1323NC .Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.233.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1Y0 X3 -I/OMultiplexed I/O & Peripheral Pin Y0 X3 - (General)
2X0～X23I/OMultiplexed I/O & Peripheral Pin X0～X23 (General)
3X6I/OMultiplexed I/O & Peripheral Pin X6 (General)
4X0～X23I/OMultiplexed I/O & Peripheral Pin X0～X23 (General)
5X8I/OMultiplexed I/O & Peripheral Pin X8 (General)
6X9I/OMultiplexed I/O & Peripheral Pin X9 (General)
7X10I/OMultiplexed I/O & Peripheral Pin X10 (General)
8X0～X23I/OMultiplexed I/O & Peripheral Pin X0～X23 (General)
9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
10P/ S -I/OMultiplexed I/O & Peripheral Pin P/ S - (General)
11X0～X23I/OMultiplexed I/O & Peripheral Pin X0～X23 (General)
12GNDGNDGround Reference Pin (GND)
13Y6I/OMultiplexed I/O & Peripheral Pin Y6 (General)
14STBI/OMultiplexed I/O & Peripheral Pin STB (General)
15Y5I/OMultiplexed I/O & Peripheral Pin Y5 (General)
16VEEI/OMultiplexed I/O & Peripheral Pin VEE (General)
17Y4I/OMultiplexed I/O & Peripheral Pin Y4 (General)
18AX1I/OMultiplexed I/O & Peripheral Pin AX1 (General)
19Y0～Y4I/OMultiplexed I/O & Peripheral Pin Y0～Y4 (General)
20Y0～Y4I/OMultiplexed I/O & Peripheral Pin Y0～Y4 (General)
21AY1I/OMultiplexed I/O & Peripheral Pin AY1 (General)
22NCI/OMultiplexed I/O & Peripheral Pin NC (General)
23NC .I/OMultiplexed I/O & Peripheral Pin NC . (General)
24X13I/OMultiplexed I/O & Peripheral Pin X13 (General)
25X12I/OMultiplexed I/O & Peripheral Pin X12 (General)
26X5I/OMultiplexed I/O & Peripheral Pin X5 (General)
27X4I/OMultiplexed I/O & Peripheral Pin X4 (General)
28X0～X23I/OMultiplexed I/O & Peripheral Pin X0～X23 (General)
29X2I/OMultiplexed I/O & Peripheral Pin X2 (General)
30X1I/OMultiplexed I/O & Peripheral Pin X1 (General)
31X0I/OMultiplexed I/O & Peripheral Pin X0 (General)
32NC .I/OMultiplexed I/O & Peripheral Pin NC . (General)
33Y0I/OMultiplexed I/O & Peripheral Pin Y0 (General)
34CS/CKI/OMultiplexed I/O & Peripheral Pin CS/CK (General)
35Y1I/OMultiplexed I/O & Peripheral Pin Y1 (General)
36DATI/OMultiplexed I/O & Peripheral Pin DAT (UART)
37Y2I/OMultiplexed I/O & Peripheral Pin Y2 (General)
38VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
39X0～X23I/OMultiplexed I/O & Peripheral Pin X0～X23 (General)
40NC .I/OMultiplexed I/O & Peripheral Pin NC . (General)
41RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
42Y0～Y4I/OMultiplexed I/O & Peripheral Pin Y0～Y4 (General)
43AX0I/OMultiplexed I/O & Peripheral Pin AX0 (General)
44NC .I/OMultiplexed I/O & Peripheral Pin NC . (General)
PIN 1 Y0 X3 -
I/O
Multiplexed I/O & Peripheral Pin Y0 X3 - (General)
Design note: Signal terminal Y0 X3 - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y0 X3 -. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH446Q (WCH · LQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH446Q (LQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH446Q (LQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH446Q (LQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH446Q (LQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH446Q (LQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH446Q (LQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH446
P2 · p02_fig01EXACT PACKAGE
CH446Q (LQFP-44(10x10)) — 封装形式 宽度 引脚间距 封装说明 订货型号 LQFP-44 10*10mm 0.8mm 31.5mil 标准LQFP44 脚贴片 CH446Q LQFP-44 10*10mm 0.8mm 31.5mil 标准LQFP44 脚贴片 CH340X
封装形式 宽度 引脚间距 封装说明 订货型号 LQFP-44 10*10mm 0.8mm 31.5mil 标准LQFP44 脚贴片 CH446Q LQFP-44 10*10mm 0.8mm 31.5mil 标准LQFP44 脚贴片 CH340X
P1 · p01_fig011486×578px
CH446Q (LQFP-44(10x10)) — CH340X 是5x24 矩阵模拟开关芯片。CH340X 包含120 只模拟开关，分布于5x24 信号通道矩阵的 各个交叉点，每只模拟开关都可以独立的开启或者关闭，从而实现5x24 信号通道的任意路由。
CH340X 是5x24 矩阵模拟开关芯片。CH340X 包含120 只模拟开关，分布于5x24 信号通道矩阵的 各个交叉点，每只模拟开关都可以独立的开启或者关闭，从而实现5x24 信号通道的任意路由。
P1 · p01_fig021486×579px
CH446Q (LQFP-44(10x10)) — 2、特点
2、特点
P1 · p01_fig01P1
CH446Q (LQFP-44(10x10)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P4 · p04_fig011540×288px
CH446Q (LQFP-44(10x10)) — 下表是CH446X 芯片7 位地址ADDR 的译码真值表，也是120 只模拟开关的编址表。
下表是CH446X 芯片7 位地址ADDR 的译码真值表，也是120 只模拟开关的编址表。
P4 · p04_fig01P4
CH446Q (LQFP-44(10x10)) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)
P7 · p07_fig011512×429px
CH446Q (LQFP-44(10x10)) — 7、应用
7、应用

Technical Specifications & Part Details (CH446Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH446Q (LQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH446 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.25 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH446Q (LQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH446Q (LQFP-44(10x10))?

Manufactured by WCH, the CH446Q is housed in a LQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch. Key pins include: 1 (Y0 X3 -: Multiplexed I/O & Peripheral Pin Y0 X3 - (General)), 2 (X0～X23: Multiplexed I/O & Peripheral Pin X0～X23 (General)), 3 (X6: Multiplexed I/O & Peripheral Pin X6 (General)), 4 (X0～X23: Multiplexed I/O & Peripheral Pin X0～X23 (General)), 5 (X8: Multiplexed I/O & Peripheral Pin X8 (General)), 6 (X9: Multiplexed I/O & Peripheral Pin X9 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH446Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH446Q (LQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH446Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH446Q (WCH, LQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & CH446 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1Y0 X3 -Digital_IOSignal terminal Y0 X3 - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y0 X3 -. Supported peripheral buses: General.
2X0～X23Digital_IOSignal terminal X0～X23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0～X23. Supported peripheral buses: General.
3X6Digital_IOSignal terminal X6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X6. Supported peripheral buses: General.
4X0～X23Digital_IOSignal terminal X0～X23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0～X23. Supported peripheral buses: General.
5X8Digital_IOSignal terminal X8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X8. Supported peripheral buses: General.
6X9Digital_IOSignal terminal X9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X9. Supported peripheral buses: General.
7X10Digital_IOSignal terminal X10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X10. Supported peripheral buses: General.
8X0～X23Digital_IOSignal terminal X0～X23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0～X23. Supported peripheral buses: General.
9NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10P/ S -Digital_IOSignal terminal P/ S - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P/ S -. Supported peripheral buses: General.
11X0～X23Digital_IOSignal terminal X0～X23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0～X23. Supported peripheral buses: General.
12GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
13Y6Digital_IOSignal terminal Y6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y6. Supported peripheral buses: General.
14STBDigital_IOSignal terminal STB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STB. Supported peripheral buses: General.
15Y5Digital_IOSignal terminal Y5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y5. Supported peripheral buses: General.
16VEEDigital_IOSignal terminal VEE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VEE. Supported peripheral buses: General.
17Y4Digital_IOSignal terminal Y4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y4. Supported peripheral buses: General.
18AX1Digital_IOSignal terminal AX1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AX1. Supported peripheral buses: General.
19Y0～Y4Digital_IOSignal terminal Y0～Y4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y0～Y4. Supported peripheral buses: General.
20Y0～Y4Digital_IOSignal terminal Y0～Y4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y0～Y4. Supported peripheral buses: General.
21AY1Digital_IOSignal terminal AY1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AY1. Supported peripheral buses: General.
22NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
23NC .Digital_IOSignal terminal NC . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC .. Supported peripheral buses: General.
24X13Digital_IOSignal terminal X13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X13. Supported peripheral buses: General.
25X12Digital_IOSignal terminal X12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X12. Supported peripheral buses: General.
26X5Digital_IOSignal terminal X5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X5. Supported peripheral buses: General.
27X4Digital_IOSignal terminal X4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X4. Supported peripheral buses: General.
28X0～X23Digital_IOSignal terminal X0～X23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0～X23. Supported peripheral buses: General.
29X2Digital_IOSignal terminal X2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X2. Supported peripheral buses: General.
30X1Digital_IOSignal terminal X1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X1. Supported peripheral buses: General.
31X0Digital_IOSignal terminal X0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0. Supported peripheral buses: General.
32NC .Digital_IOSignal terminal NC . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC .. Supported peripheral buses: General.
33Y0Digital_IOSignal terminal Y0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y0. Supported peripheral buses: General.
34CS/CKDigital_IOSignal terminal CS/CK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS/CK. Supported peripheral buses: General.
35Y1Digital_IOSignal terminal Y1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y1. Supported peripheral buses: General.
36DATDigital_IOSignal terminal DAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DAT. Supported peripheral buses: UART.
37Y2Digital_IOSignal terminal Y2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y2. Supported peripheral buses: General.
38VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
39X0～X23Digital_IOSignal terminal X0～X23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X0～X23. Supported peripheral buses: General.
40NC .Digital_IOSignal terminal NC . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC .. Supported peripheral buses: General.
41RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
42Y0～Y4Digital_IOSignal terminal Y0～Y4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Y0～Y4. Supported peripheral buses: General.
43AX0Digital_IOSignal terminal AX0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AX0. Supported peripheral buses: General.
44NC .Digital_IOSignal terminal NC . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC .. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload