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CH317Q (LQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH317Q

WCHID: C109469LQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH317Q (LQFP-44(10x10))1VCC182XI3XO4VCC33U5GND6RES7D-8D+9VCC33U10GND11VCC1812VCC1813GND14RXD015RXD116RXD217RXD318RXDV19VCC1820GND21RXCK22VCC3344GND43VCC3342MOD241VCC3340GND39VCC1838MOD037MDIO36MDC35TXD034TXD133TXD232TXD331VCC3330GND29VCC1828TXEN27TXCK26NC25GND24NC23NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.233.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
2XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
3XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
4VCC33UPowerPower Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)
5GNDGNDGround Reference Pin (GND)
6RESI/OMultiplexed I/O & Peripheral Pin RES (General)
7D-I/OMultiplexed I/O & Peripheral Pin D- (USB)
8D+I/OMultiplexed I/O & Peripheral Pin D+ (USB)
9VCC33UPowerPower Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)
10GNDGNDGround Reference Pin (GND)
11VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
12VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
13GNDGNDGround Reference Pin (GND)
14RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
15RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
16RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
17RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
18RXDVI/OMultiplexed I/O & Peripheral Pin RXDV (UART)
19VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
20GNDGNDGround Reference Pin (GND)
21RXCKI/OMultiplexed I/O & Peripheral Pin RXCK (General)
22VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
23NCI/OMultiplexed I/O & Peripheral Pin NC (General)
24NCI/OMultiplexed I/O & Peripheral Pin NC (General)
25GNDGNDGround Reference Pin (GND)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27TXCKI/OMultiplexed I/O & Peripheral Pin TXCK (General)
28TXENI/OMultiplexed I/O & Peripheral Pin TXEN (General)
29VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
30GNDGNDGround Reference Pin (GND)
31VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
32TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
33TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
34TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
35TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
36MDCI/OMultiplexed I/O & Peripheral Pin MDC (General)
37MDIOI/OMultiplexed I/O & Peripheral Pin MDIO (General)
38MOD0I/OMultiplexed I/O & Peripheral Pin MOD0 (General)
39VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
40GNDGNDGround Reference Pin (GND)
41VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
42MOD2I/OMultiplexed I/O & Peripheral Pin MOD2 (General)
43VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
44GNDGNDGround Reference Pin (GND)
PIN 1 VCC18
Power
Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 2 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH317Q (WCH · LQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH317Q (LQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH317Q (LQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH317Q (LQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH317Q (LQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH317Q (LQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH317Q (LQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (2 figures · Page 1/1)
Showing 1–2 of 2 uncropped original figures for CH317
P1 · p01_fig011626×478px
CH317Q (LQFP-44(10x10)) — Figure 1 Block diagram of network cable extension scheme
Figure 1 Block diagram of network cable extension scheme
P1 · p01_fig021626×505px
CH317Q (LQFP-44(10x10)) — Figure 2 Block diagram of optical fiber extension scheme
Figure 2 Block diagram of optical fiber extension scheme

Technical Specifications & Part Details (CH317Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH317Q (LQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH317Q (LQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH317Q (LQFP-44(10x10))?

Manufactured by WCH, the CH317Q is housed in a LQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch. Key pins include: 1 (VCC18: Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)), 2 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 3 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)), 4 (VCC33U: Power Supply Input (VCC33U — 3.3V / 5.0V Standard Logic)), 5 (GND: Ground Reference Pin (GND)), 6 (RES: Multiplexed I/O & Peripheral Pin RES (General)).

What are the IPC-7351B PCB Footprint dimensions for CH317Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH317Q (LQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH317Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH317Q (WCH, LQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & CH317 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
3XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
4VCC33UPower_InPrimary positive power supply input (VCC33U) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6RESDigital_IOSignal terminal RES (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RES. Supported peripheral buses: General.
7D-Digital_IOSignal terminal D- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D-. Supported peripheral buses: USB.
8D+Digital_IOSignal terminal D+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D+. Supported peripheral buses: USB.
9VCC33UPower_InPrimary positive power supply input (VCC33U) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
15RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
16RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
17RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
18RXDVDigital_IOSignal terminal RXDV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXDV. Supported peripheral buses: UART.
19VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21RXCKDigital_IOSignal terminal RXCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXCK. Supported peripheral buses: General.
22VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
24NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
26NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27TXCKDigital_IOSignal terminal TXCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXCK. Supported peripheral buses: General.
28TXENDigital_IOSignal terminal TXEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXEN. Supported peripheral buses: General.
29VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
31VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
32TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
33TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
34TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
35TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
36MDCDigital_IOSignal terminal MDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General.
37MDIODigital_IOSignal terminal MDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General.
38MOD0Digital_IOSignal terminal MOD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOD0. Supported peripheral buses: General.
39VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
40GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
41VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
42MOD2Digital_IOSignal terminal MOD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOD2. Supported peripheral buses: General.
43VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
44GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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