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CH340S (SOP-28-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH340S

WCHID: C109467SOP-28-300mil · 28 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH340S (SOP-28-300mil)1NOS#2RSTI3SIN#4AFD#5ERR#6PEMP7ACK#8SLCT9V310UD+11UD-12GND13XI14XO28VCC27BUSY26INI#25STB#24C34123PRT#22D721D620D519D418D317D216D115D0Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=7.50mm · Pitch e=1.27mmD=17.90mm-10-8-6-4-20246810131197531-1-3-5-7-9-11-13mm
3. 3D CAD MODEL
Package Body: 7.50mm × 17.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NOS#I/OMultiplexed I/O & Peripheral Pin NOS# (USB)
2RSTII/OMultiplexed I/O & Peripheral Pin RSTI (General)
3SIN#I/OMultiplexed I/O & Peripheral Pin SIN# (General)
4AFD#I/OMultiplexed I/O & Peripheral Pin AFD# (General)
5ERR#I/OMultiplexed I/O & Peripheral Pin ERR# (General)
6PEMPI/OMultiplexed I/O & Peripheral Pin PEMP (General)
7ACK#I/OMultiplexed I/O & Peripheral Pin ACK# (General)
8SLCTI/OMultiplexed I/O & Peripheral Pin SLCT (General)
9V3PowerInternal 3.3V USB Transceiver Supply / LDO Bypass (V3)
10UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB, UART)
11UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB, UART)
12GNDGNDGround Reference Pin (GND)
13XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
14XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
15D0I/OMultiplexed I/O & Peripheral Pin D0 (USB, UART)
16D1I/OMultiplexed I/O & Peripheral Pin D1 (USB, UART)
17D2I/OMultiplexed I/O & Peripheral Pin D2 (USB, UART)
18D3I/OMultiplexed I/O & Peripheral Pin D3 (USB, UART)
19D4I/OMultiplexed I/O & Peripheral Pin D4 (USB, UART)
20D5I/OMultiplexed I/O & Peripheral Pin D5 (USB, UART)
21D6I/OMultiplexed I/O & Peripheral Pin D6 (USB, UART)
22D7I/OMultiplexed I/O & Peripheral Pin D7 (USB, UART)
23PRT#I/OMultiplexed I/O & Peripheral Pin PRT# (General)
24C341I/OMultiplexed I/O & Peripheral Pin C341 (General)
25STB#I/OMultiplexed I/O & Peripheral Pin STB# (General)
26INI#I/OMultiplexed I/O & Peripheral Pin INI# (General)
27BUSYI/OMultiplexed I/O & Peripheral Pin BUSY (General)
28VCCPowerPower Supply Input (VCC — 3.3V / 5.0V USB-UART Domain)
PIN 1 NOS#
I/O
Multiplexed I/O & Peripheral Pin NOS# (USB)
Design note: 禁止USB设备挂起 低有效 内置上拉电阻 ， ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH340S (WCH · SOP-28-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH340S (SOP-28-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH340S (SOP-28-300mil) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH340S (SOP-28-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH340S (SOP-28-300mil) - 4. Package Dimensions (D×E×A)
SOP-28-300mil · 7.50×17.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH340S (SOP-28-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH340S (SOP-28-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH340
P1 · p01_fig02EXACT PACKAGE
CH340S (SOP-28-300mil) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOP-28 7.62mm 300mil 1.27mm 50mil 标准的28 脚贴片 CH340H SOP-28 7.62mm 300mil 1.27mm 50mil 标准的28 脚贴片 CH340S 型号区别：CH340H 内置时钟，无需外部晶振。
封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOP-28 7.62mm 300mil 1.27mm 50mil 标准的28 脚贴片 CH340H SOP-28 7.62mm 300mil 1.27mm 50mil 标准的28 脚贴片 CH340S 型号区别：CH340H 内置时钟，无需外部晶振。
P1 · p01_fig011680×656px
CH340S (SOP-28-300mil) — CH340 是一个USB 总线的转接芯片，实现USB 转串口或者USB 转打印口。 在打印口方式下，CH340 提供了兼容USB 规范和Windows 操作系统的标准USB 打印口，用于将普 通的并口打印机直接升级到USB 总线。有关USB 转串口的说明请参考手册（一）CH340DS1。 | 2、特点 | 异步串口/UART/RS232/RS485 | 转换并口打印机为USB 打印机 | USB | 计算机 | 或者 其它 USB 主机 | CH340 转接芯片
CH340 是一个USB 总线的转接芯片，实现USB 转串口或者USB 转打印口。 在打印口方式下，CH340 提供了兼容USB 规范和Windows 操作系统的标准USB 打印口，用于将普 通的并口打印机直接升级到USB 总线。有关USB 转串口的说明请参考手册（一）CH340DS1。 | 2、特点 | 异步串口/UART/RS232/RS485 | 转换并口打印机为USB 打印机 | USB | 计算机 | 或者 其它 USB 主机 | CH340 转接芯片
P1 · p01_fig02P1
CH340S (SOP-28-300mil) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P4 · p04_fig011409×510px
CH340S (SOP-28-300mil) — 6.3. 时序参数（测试条件：TA=25℃，VCC=5V，参考附图）
6.3. 时序参数（测试条件：TA=25℃，VCC=5V，参考附图）
P4 · p04_fig01P4
CH340S (SOP-28-300mil) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)
P5 · p05_fig011387×634px
CH340S (SOP-28-300mil) — 上图中PRT#引脚接地（或者PRT#引脚连接C341 引脚）将CH340 配置为打印口模式，用于将并口 打印机转换为USB 打印机。图中P10 端口的信号线对应于IEEE-1284 规范或标准Centronic 打印机接 口的信号线，DB36 端口P10 可以直接连接原并口打印机。
上图中PRT#引脚接地（或者PRT#引脚连接C341 引脚）将CH340 配置为打印口模式，用于将并口 打印机转换为USB 打印机。图中P10 端口的信号线对应于IEEE-1284 规范或标准Centronic 打印机接 口的信号线，DB36 端口P10 可以直接连接原并口打印机。

Technical Specifications & Part Details (CH340S)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Interface Bridge / Precision Clock & Timer IC
Detailed Overview:CH340S (SOP-28-300mil) is a 28-pin interface bridge / precision clock & timer ic featuring a 17.90 × 7.50 × 2.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
USB 2.0 Full-Speed 12 Mbps (UART 50 bps ~ 2 Mbps)
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
17.90 × 7.50 × 2.50 mm (A1=0.20 mm)
Package family: SOP (SOP-28-300mil)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-28-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
17.90 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1
BOM
100nF (0.1µF) 50V X7R
0402 / 0603
Internal 3.3V LDO cap at V3 (Pin 4) — to GND at VCC=5V, or tie V3 directly to VCC at 3.3V.
C2, C3
BOM
100nF + 10µF
0603
Main VCC supply decoupling (Pin 16) from USB VBUS — place < 2mm from Pin 16.
Y1 + C4, C5
BOM
12MHz Crystal + 2× 22pF NP0
HC-49S / SMD-3225 + 0603
Mandatory 12MHz crystal for CH340G (Pins 7/8) — switch to CH340C to eliminate this crystal.
CH340C
WCH
100% Drop-in100% Pin-to-Pin SOP-16 (Built-in 12MHz clock) — shares SOP-16 PCB footprint with CH340G; leave Y1/22pF DNI.
CH340G
WCH
100% Drop-in100% Pin-to-Pin SOP-16 — requires external 12MHz crystal + two 22pF load caps on Pins 7-8.
CH340B
WCH
100% Drop-in100% Pin-to-Pin SOP-16 (Built-in 12MHz clock) — shares SOP-16 PCB footprint with CH340G; leave Y1/22pF DNI.

Technical Frequently Asked Questions (FAQ) — CH340S (SOP-28-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH340S (SOP-28-300mil)?

Manufactured by WCH, the CH340S is housed in a SOP-28-300mil package with 28 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (NOS#: Multiplexed I/O & Peripheral Pin NOS# (USB)), 2 (RSTI: Multiplexed I/O & Peripheral Pin RSTI (General)), 3 (SIN#: Multiplexed I/O & Peripheral Pin SIN# (General)), 4 (AFD#: Multiplexed I/O & Peripheral Pin AFD# (General)), 5 (ERR#: Multiplexed I/O & Peripheral Pin ERR# (General)), 6 (PEMP: Multiplexed I/O & Peripheral Pin PEMP (General)).

What are the IPC-7351B PCB Footprint dimensions for CH340S?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH340S (SOP-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH340S?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH340S (WCH, SOP-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & CH340 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NOS#Digital_IOSignal terminal NOS# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: NOS#. Supported peripheral buses: USB.
2RSTIDigital_IOSignal terminal RSTI (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General.
3SIN#Digital_IOSignal terminal SIN# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: SIN#. Supported peripheral buses: General.
4AFD#Digital_IOSignal terminal AFD# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: AFD#. Supported peripheral buses: General.
5ERR#Digital_IOSignal terminal ERR# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: ERR#. Supported peripheral buses: General.
6PEMPDigital_IOSignal terminal PEMP (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: PEMP. Supported peripheral buses: General.
7ACK#Digital_IOSignal terminal ACK# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: ACK#. Supported peripheral buses: General.
8SLCTDigital_IOSignal terminal SLCT (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: SLCT. Supported peripheral buses: General.
9V3Power_OutInternal 3.3V LDO regulator node supplying the USB transceiver and clock generator.
10UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB, UART.
11UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB, UART.
12GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
13XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
14XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
15D0Digital_IOSignal terminal D0 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D0. Supported peripheral buses: USB, UART.
16D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D1. Supported peripheral buses: USB, UART.
17D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D2. Supported peripheral buses: USB, UART.
18D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D3. Supported peripheral buses: USB, UART.
19D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D4. Supported peripheral buses: USB, UART.
20D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D5. Supported peripheral buses: USB, UART.
21D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D6. Supported peripheral buses: USB, UART.
22D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: D7. Supported peripheral buses: USB, UART.
23PRT#Digital_IOSignal terminal PRT# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: PRT#. Supported peripheral buses: General.
24C341Digital_IOSignal terminal C341 (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: C341. Supported peripheral buses: General.
25STB#Digital_IOSignal terminal STB# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: STB#. Supported peripheral buses: General.
26INI#Digital_IOSignal terminal INI# (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: INI#. Supported peripheral buses: General.
27BUSYDigital_IOSignal terminal BUSY (I/O, 3.3V / 5.0V USB-UART Domain domain). Multiplexed alternate functions: BUSY. Supported peripheral buses: General.
28VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V USB-UART Domain domain (Max rating: 5.5V).
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