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EEC1005-I/SX1-UB1 (WFBGA-84) — Symbol, Footprint IPC-7351B & 3D STEP Model

EEC1005-I/SX1-UB1

MICROCHIPID: C1020290WFBGA-84 · 84 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · EEC1005-I/SX1-UB1 (WFBGA-84)A1DFC_00PWRDISA2BMC_I2CSDA_A3BMC_I2CSCL_A4DFC_14IFDETNA5DFC_13IFDETNA6RSVDA7NCA8SGPIO_03DATAA9DFC_07IFDETNA10DFC_13ACTIVIB1DFC_06ACTIVIB2SGPIO_00CLOCB3DFC 05_LEDSTB4DFC_01IFDETNB5DFC_12IFDETNB6NCB7DFC_09PRSNTNB8DFC_03PWRDISB9DFC_05PWRDISB10DFC_04PWRDISC1DFC_01PWRDISC2SGPIO_03CLOCC5DFC_13PRSNTNC6RSVDC9DFC_02ACTIVIC10DFC_10ACTIVID1VCCD2DFC_07ACTIVID4nRESET_IND5SGPIO_02LOADD6DFC_12PWRDISD7NCD9DFC_08IFDETND10DFC_11ACTIVIE1BMC_2WIRERESE2DFC_15ACTIVIE3DFC_02PWRDISE4SGPIO_00DATAE7VCCE8VSSE9SGPIO_01DATAE10DFC_09ACTIVIK10DFC 08_LEDACK9DFC 09_LEDACK8DFC 07_LEDACK7DFC 06_LEDACK6DFC 12_LEDSTK5DFC 13_LEDACK4DFC 02_LEDACK3DFC_15PRSNTNK2DFC_00PRSNTNK1CONFIG_BPNUMJ10DFC_12PRSNTNJ9NCJ8SGPIO_02DATAJ7DFC 12_LEDACJ6DFC 15_LEDACJ5DFC 03_LEDACJ4DFC_10IFDETNJ3DFC_03IFDETNJ2DFC_00IFDETNJ1DFC_04IFDETNH10DFC 10_LEDSTH9DFC 09_LEDSTH6VCCH5DFC_10PWRDISH2DFC_05IFDETNH1CONFIG_PING10DFC 08_LEDSTG9HEARTBEAT_PIG7DFC_04ACTIVIG6VSSG5VSSG4DFC_12ACTIVIG2VREF_ADCG1DFC_15PWRDISF10nSTRAP_INF9DFC_07PRSNTNF8VSSF7DFC 04_LEDSTF4SGPIO_01LOADF3SGPIO_03DATAF2DFC_06PWRDISF1VR_CAPGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.858.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4mm
2. 2D FOOTPRINT
K1K10K8K9K6K7K4K5K3K2J1J10J8J9J6J7J4J5J3J2H1H10H9H6H5H2G1G10G9G6G7G4G5G2F1F10F8F9F7F4F3F2E1E10E8E9E7E4E3E2D1D10D9D6D7D4D5D2C1C10C9C6C5C2B2B3B5B4B7B6B9B8B10A10A8A9A6A7A4A5A3B1A2A1E=7.00mm · Pitch e=0.65mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (84/84)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1DFC_00PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_00PWRDISABLE__ (General)
A2BMC_I2CSDA_I/OMultiplexed I/O & Peripheral Pin BMC_I2CSDA_ (I2C)
A3BMC_I2CSCL_I/OMultiplexed I/O & Peripheral Pin BMC_I2CSCL_ (I2C)
A4DFC_14IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_14IFDETN__ (General)
A5DFC_13IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_13IFDETN__ (General)
A6RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
A7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
A8SGPIO_03DATAOUT_I/OMultiplexed I/O & Peripheral Pin SGPIO_03DATAOUT_ (General)
A9DFC_07IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_07IFDETN__ (General)
A10DFC_13ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_13ACTIVITYN__ (General)
B1DFC_06ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_06ACTIVITYN__ (General)
B2SGPIO_00CLOCK_I/OMultiplexed I/O & Peripheral Pin SGPIO_00CLOCK_ (General)
B3DFC 05_LEDSTAN___I/OMultiplexed I/O & Peripheral Pin DFC 05_LEDSTAN___ (General)
B4DFC_01IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_01IFDETN__ (General)
B5DFC_12IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_12IFDETN__ (General)
B6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
B7DFC_09PRSNTN__I/OMultiplexed I/O & Peripheral Pin DFC_09PRSNTN__ (General)
B8DFC_03PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_03PWRDISABLE__ (General)
B9DFC_05PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_05PWRDISABLE__ (General)
B10DFC_04PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_04PWRDISABLE__ (General)
C1DFC_01PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_01PWRDISABLE__ (General)
C2SGPIO_03CLOCK_I/OMultiplexed I/O & Peripheral Pin SGPIO_03CLOCK_ (General)
C5DFC_13PRSNTN__I/OMultiplexed I/O & Peripheral Pin DFC_13PRSNTN__ (General)
C6RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
C9DFC_02ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_02ACTIVITYN__ (General)
C10DFC_10ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_10ACTIVITYN__ (General)
D1VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
D2DFC_07ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_07ACTIVITYN__ (General)
D4nRESET_INISystem Enable & Hardware Reset (nRESET_IN)
D5SGPIO_02LOAD_I/OMultiplexed I/O & Peripheral Pin SGPIO_02LOAD_ (General)
D6DFC_12PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_12PWRDISABLE__ (General)
D7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
D9DFC_08IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_08IFDETN__ (General)
D10DFC_11ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_11ACTIVITYN__ (General)
E1BMC_2WIRERESET_ISystem Enable & Hardware Reset (BMC_2WIRERESET_)
E2DFC_15ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_15ACTIVITYN__ (General)
E3DFC_02PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_02PWRDISABLE__ (General)
E4SGPIO_00DATAOUT_I/OMultiplexed I/O & Peripheral Pin SGPIO_00DATAOUT_ (General)
E7VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
E8VSSGNDGround Reference Pin (VSS)
E9SGPIO_01DATAOUT_I/OMultiplexed I/O & Peripheral Pin SGPIO_01DATAOUT_ (General)
E10DFC_09ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_09ACTIVITYN__ (General)
F1VR_CAPI/OMultiplexed I/O & Peripheral Pin VR_CAP (General)
F2DFC_06PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_06PWRDISABLE__ (General)
F3SGPIO_03DATAIN_AnalogMultiplexed I/O & Peripheral Pin SGPIO_03DATAIN_ (General)
F4SGPIO_01LOAD_I/OMultiplexed I/O & Peripheral Pin SGPIO_01LOAD_ (General)
F7DFC 04_LEDSTAN___I/OMultiplexed I/O & Peripheral Pin DFC 04_LEDSTAN___ (General)
F8VSSGNDGround Reference Pin (VSS)
F9DFC_07PRSNTN__I/OMultiplexed I/O & Peripheral Pin DFC_07PRSNTN__ (General)
F10nSTRAP_INI/OMultiplexed I/O & Peripheral Pin nSTRAP_IN (General)
G1DFC_15PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_15PWRDISABLE__ (General)
G2VREF_ADCI/OMultiplexed I/O & Peripheral Pin VREF_ADC (ADC)
G4DFC_12ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_12ACTIVITYN__ (General)
G5VSSGNDGround Reference Pin (VSS)
G6VSSGNDGround Reference Pin (VSS)
G7DFC_04ACTIVITYN__I/OMultiplexed I/O & Peripheral Pin DFC_04ACTIVITYN__ (General)
G9HEARTBEAT_PINI/OMultiplexed I/O & Peripheral Pin HEARTBEAT_PIN (General)
G10DFC 08_LEDSTAN___I/OMultiplexed I/O & Peripheral Pin DFC 08_LEDSTAN___ (General)
H1CONFIG_PINI/OMultiplexed I/O & Peripheral Pin CONFIG_PIN (General)
H2DFC_05IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_05IFDETN__ (General)
H5DFC_10PWRDISABLE__I/OMultiplexed I/O & Peripheral Pin DFC_10PWRDISABLE__ (General)
H6VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
H9DFC 09_LEDSTAN___I/OMultiplexed I/O & Peripheral Pin DFC 09_LEDSTAN___ (General)
H10DFC 10_LEDSTAN___I/OMultiplexed I/O & Peripheral Pin DFC 10_LEDSTAN___ (General)
J1DFC_04IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_04IFDETN__ (General)
J2DFC_00IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_00IFDETN__ (General)
J3DFC_03IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_03IFDETN__ (General)
J4DFC_10IFDETN__I/OMultiplexed I/O & Peripheral Pin DFC_10IFDETN__ (General)
J5DFC 03_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 03_LEDACTN___ (General)
J6DFC 15_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 15_LEDACTN___ (General)
J7DFC 12_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 12_LEDACTN___ (General)
J8SGPIO_02DATAIN_AnalogMultiplexed I/O & Peripheral Pin SGPIO_02DATAIN_ (General)
J9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
J10DFC_12PRSNTN__I/OMultiplexed I/O & Peripheral Pin DFC_12PRSNTN__ (General)
K1CONFIG_BPNUMPIN_I/OMultiplexed I/O & Peripheral Pin CONFIG_BPNUMPIN_ (General)
K2DFC_00PRSNTN__I/OMultiplexed I/O & Peripheral Pin DFC_00PRSNTN__ (General)
K3DFC_15PRSNTN__I/OMultiplexed I/O & Peripheral Pin DFC_15PRSNTN__ (General)
K4DFC 02_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 02_LEDACTN___ (General)
K5DFC 13_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 13_LEDACTN___ (General)
K6DFC 12_LEDSTAN___I/OMultiplexed I/O & Peripheral Pin DFC 12_LEDSTAN___ (General)
K7DFC 06_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 06_LEDACTN___ (General)
K8DFC 07_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 07_LEDACTN___ (General)
K9DFC 09_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 09_LEDACTN___ (General)
K10DFC 08_LEDACTN___AnalogMultiplexed I/O & Peripheral Pin DFC 08_LEDACTN___ (General)
PIN A1 DFC_00PWRDISABLE__
I/O
Multiplexed I/O & Peripheral Pin DFC_00PWRDISABLE__ (General)
Design note: DFC_00PWRDISABLE__
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: EEC1005-I/SX1-UB1 (MICROCHIP · WFBGA-84)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
EEC1005-I/SX1-UB1 (WFBGA-84) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
EEC1005-I/SX1-UB1 (WFBGA-84) - 2. Standard Pinout (Top View)
True package pinout (84 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
EEC1005-I/SX1-UB1 (WFBGA-84) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
EEC1005-I/SX1-UB1 (WFBGA-84) - 4. Package Dimensions (D×E×A)
WFBGA-84 · 7.00×7.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
EEC1005-I/SX1-UB1 (WFBGA-84) - 5. Recommended Land Pattern
IPC-7351B Footprint (84 Pads)Expand ›
6. Application SchematicSCHEMATIC
EEC1005-I/SX1-UB1 (WFBGA-84) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for EEC1005
P1 · p01_fig01377×200px
EEC1005-I/SX1-UB1 (WFBGA-84) — Enterprise Storage Backplane Management Processor
Enterprise Storage Backplane Management Processor
P9 · p09_fig01767×998px
EEC1005-I/SX1-UB1 (WFBGA-84) — FIGURE 3-1: VOLTAGE DIVIDER AT ADC INPUT
FIGURE 3-1: VOLTAGE DIVIDER AT ADC INPUT
P9 · p09_fig01P9
EEC1005-I/SX1-UB1 (WFBGA-84) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P48 · p48_fig011787×2734px
EEC1005-I/SX1-UB1 (WFBGA-84) — EEC1005 | DS00003392B-page 48  2020 Microchip Technology Inc. | 12.0 PACKAGE INFORMATION | 12.1 144 Pin WFBGA/WC Package | Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.micro- chip.com
EEC1005 | DS00003392B-page 48  2020 Microchip Technology Inc. | 12.0 PACKAGE INFORMATION | 12.1 144 Pin WFBGA/WC Package | Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.micro- chip.com
P48 · p48_fig01P48
EEC1005-I/SX1-UB1 (WFBGA-84) — Datasheet Page 48 (p48_fig01)
Datasheet Page 48 (p48_fig01)

Technical Specifications & Part Details (EEC1005-I/SX1-UB1)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:EEC1005-I/SX1-UB1 (WFBGA-84) is a 84-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.35 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C, ADC interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-84)
Pin Count & Lead PitchN / e
84 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C, ADC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol84 auto-grouped pins
OK
IPC-7351B Land Pattern84 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WFBGA-84)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.65mm
Pad Size (W × L)Level B
0.35 × 0.35 mm
Pins / Total PadsTopology
84P / 84Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WFBGA-84
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — EEC1005-I/SX1-UB1 (WFBGA-84)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of EEC1005-I/SX1-UB1 (WFBGA-84)?

Manufactured by MICROCHIP, the EEC1005-I/SX1-UB1 is housed in a WFBGA-84 package with 84 pins and a 0.65 mm lead pitch. Key pins include: A1 (DFC_00PWRDISABLE__: Multiplexed I/O & Peripheral Pin DFC_00PWRDISABLE__ (General)), A2 (BMC_I2CSDA_: Multiplexed I/O & Peripheral Pin BMC_I2CSDA_ (I2C)), A3 (BMC_I2CSCL_: Multiplexed I/O & Peripheral Pin BMC_I2CSCL_ (I2C)), A4 (DFC_14IFDETN__: Multiplexed I/O & Peripheral Pin DFC_14IFDETN__ (General)), A5 (DFC_13IFDETN__: Multiplexed I/O & Peripheral Pin DFC_13IFDETN__ (General)), A6 (RSVD: Multiplexed I/O & Peripheral Pin RSVD (General)).

What are the IPC-7351B PCB Footprint dimensions for EEC1005-I/SX1-UB1?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), EEC1005-I/SX1-UB1 (WFBGA-84) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.65 mm, and 84 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for EEC1005-I/SX1-UB1?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for EEC1005-I/SX1-UB1 (MICROCHIP, WFBGA-84) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (84 pins) & EEC1005 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1DFC_00PWRDISABLE__Digital_IOSignal terminal DFC_00PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_00PWRDISABLE__. Supported peripheral buses: General.
A2BMC_I2CSDA_Digital_IOSignal terminal BMC_I2CSDA_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BMC_I2CSDA_. Supported peripheral buses: I2C.
A3BMC_I2CSCL_Digital_IOSignal terminal BMC_I2CSCL_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BMC_I2CSCL_. Supported peripheral buses: I2C.
A4DFC_14IFDETN__Digital_IOSignal terminal DFC_14IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_14IFDETN__. Supported peripheral buses: General.
A5DFC_13IFDETN__Digital_IOSignal terminal DFC_13IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_13IFDETN__. Supported peripheral buses: General.
A6RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
A7NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
A8SGPIO_03DATAOUT_Digital_IOSignal terminal SGPIO_03DATAOUT_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_03DATAOUT_. Supported peripheral buses: General.
A9DFC_07IFDETN__Digital_IOSignal terminal DFC_07IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_07IFDETN__. Supported peripheral buses: General.
A10DFC_13ACTIVITYN__Digital_IOSignal terminal DFC_13ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_13ACTIVITYN__. Supported peripheral buses: General.
B1DFC_06ACTIVITYN__Digital_IOSignal terminal DFC_06ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_06ACTIVITYN__. Supported peripheral buses: General.
B2SGPIO_00CLOCK_Digital_IOSignal terminal SGPIO_00CLOCK_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_00CLOCK_. Supported peripheral buses: General.
B3DFC 05_LEDSTAN___Digital_IOSignal terminal DFC 05_LEDSTAN___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC 05_LEDSTAN___. Supported peripheral buses: General.
B4DFC_01IFDETN__Digital_IOSignal terminal DFC_01IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_01IFDETN__. Supported peripheral buses: General.
B5DFC_12IFDETN__Digital_IOSignal terminal DFC_12IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_12IFDETN__. Supported peripheral buses: General.
B6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
B7DFC_09PRSNTN__Digital_IOSignal terminal DFC_09PRSNTN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_09PRSNTN__. Supported peripheral buses: General.
B8DFC_03PWRDISABLE__Digital_IOSignal terminal DFC_03PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_03PWRDISABLE__. Supported peripheral buses: General.
B9DFC_05PWRDISABLE__Digital_IOSignal terminal DFC_05PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_05PWRDISABLE__. Supported peripheral buses: General.
B10DFC_04PWRDISABLE__Digital_IOSignal terminal DFC_04PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_04PWRDISABLE__. Supported peripheral buses: General.
C1DFC_01PWRDISABLE__Digital_IOSignal terminal DFC_01PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_01PWRDISABLE__. Supported peripheral buses: General.
C2SGPIO_03CLOCK_Digital_IOSignal terminal SGPIO_03CLOCK_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_03CLOCK_. Supported peripheral buses: General.
C5DFC_13PRSNTN__Digital_IOSignal terminal DFC_13PRSNTN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_13PRSNTN__. Supported peripheral buses: General.
C6RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
C9DFC_02ACTIVITYN__Digital_IOSignal terminal DFC_02ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_02ACTIVITYN__. Supported peripheral buses: General.
C10DFC_10ACTIVITYN__Digital_IOSignal terminal DFC_10ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_10ACTIVITYN__. Supported peripheral buses: General.
D1VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D2DFC_07ACTIVITYN__Digital_IOSignal terminal DFC_07ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_07ACTIVITYN__. Supported peripheral buses: General.
D4nRESET_INDigital_IOActive-low hardware reset terminal (nRESET_IN): pulling this pin Low resets the processor core and peripherals.
D5SGPIO_02LOAD_Digital_IOSignal terminal SGPIO_02LOAD_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_02LOAD_. Supported peripheral buses: General.
D6DFC_12PWRDISABLE__Digital_IOSignal terminal DFC_12PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_12PWRDISABLE__. Supported peripheral buses: General.
D7NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
D9DFC_08IFDETN__Digital_IOSignal terminal DFC_08IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_08IFDETN__. Supported peripheral buses: General.
D10DFC_11ACTIVITYN__Digital_IOSignal terminal DFC_11ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_11ACTIVITYN__. Supported peripheral buses: General.
E1BMC_2WIRERESET_Digital_IOActive-low hardware reset terminal (BMC_2WIRERESET_): pulling this pin Low resets the processor core and peripherals.
E2DFC_15ACTIVITYN__Digital_IOSignal terminal DFC_15ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_15ACTIVITYN__. Supported peripheral buses: General.
E3DFC_02PWRDISABLE__Digital_IOSignal terminal DFC_02PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_02PWRDISABLE__. Supported peripheral buses: General.
E4SGPIO_00DATAOUT_Digital_IOSignal terminal SGPIO_00DATAOUT_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_00DATAOUT_. Supported peripheral buses: General.
E7VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9SGPIO_01DATAOUT_Digital_IOSignal terminal SGPIO_01DATAOUT_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_01DATAOUT_. Supported peripheral buses: General.
E10DFC_09ACTIVITYN__Digital_IOSignal terminal DFC_09ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_09ACTIVITYN__. Supported peripheral buses: General.
F1VR_CAPDigital_IOSignal terminal VR_CAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VR_CAP. Supported peripheral buses: General.
F2DFC_06PWRDISABLE__Digital_IOSignal terminal DFC_06PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_06PWRDISABLE__. Supported peripheral buses: General.
F3SGPIO_03DATAIN_AnalogSignal terminal SGPIO_03DATAIN_ (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_03DATAIN_. Supported peripheral buses: General.
F4SGPIO_01LOAD_Digital_IOSignal terminal SGPIO_01LOAD_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SGPIO_01LOAD_. Supported peripheral buses: General.
F7DFC 04_LEDSTAN___Digital_IOSignal terminal DFC 04_LEDSTAN___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC 04_LEDSTAN___. Supported peripheral buses: General.
F8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F9DFC_07PRSNTN__Digital_IOSignal terminal DFC_07PRSNTN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_07PRSNTN__. Supported peripheral buses: General.
F10nSTRAP_INDigital_IOSignal terminal nSTRAP_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nSTRAP_IN. Supported peripheral buses: General.
G1DFC_15PWRDISABLE__Digital_IOSignal terminal DFC_15PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_15PWRDISABLE__. Supported peripheral buses: General.
G2VREF_ADCAnalogSignal terminal VREF_ADC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF_ADC. Supported peripheral buses: ADC.
G4DFC_12ACTIVITYN__Digital_IOSignal terminal DFC_12ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_12ACTIVITYN__. Supported peripheral buses: General.
G5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G7DFC_04ACTIVITYN__Digital_IOSignal terminal DFC_04ACTIVITYN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_04ACTIVITYN__. Supported peripheral buses: General.
G9HEARTBEAT_PINDigital_IOSignal terminal HEARTBEAT_PIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HEARTBEAT_PIN. Supported peripheral buses: General.
G10DFC 08_LEDSTAN___Digital_IOSignal terminal DFC 08_LEDSTAN___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC 08_LEDSTAN___. Supported peripheral buses: General.
H1CONFIG_PINDigital_IOSignal terminal CONFIG_PIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CONFIG_PIN. Supported peripheral buses: General.
H2DFC_05IFDETN__Digital_IOSignal terminal DFC_05IFDETN__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_05IFDETN__. Supported peripheral buses: General.
H5DFC_10PWRDISABLE__Digital_IOSignal terminal DFC_10PWRDISABLE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC_10PWRDISABLE__. Supported peripheral buses: General.
H6VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H9DFC 09_LEDSTAN___Digital_IOSignal terminal DFC 09_LEDSTAN___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC 09_LEDSTAN___. Supported peripheral buses: General.
H10DFC 10_LEDSTAN___Digital_IOSignal terminal DFC 10_LEDSTAN___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFC 10_LEDSTAN___. Supported peripheral buses: General.
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